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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16635
240-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64 GRAY SCALES)
The PD16635 is a source driver for TFT-LCDs capable of dealing with displays with 64 gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as 11.5 VP-P, level inversion operation of the LCD's common electrode is rendered unnecessary. Also, to be able to deal with full-dot inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 33 MHz when driving at 3.0 V, this driver is applicable to SVGA-standard TFT-LCD panels.
FEATURES
* Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter * Output dynamic range 11.5 VP-P min. (@ VDD2 = 13.5 V) * CMOS level input * Input of 6 bits (gradation data) by 6 dots * High-speed data transfer: fmax. = 33 MHz (internal data transfer speed when operating at 3.0 V) * 240 outputs * Dedicaded full-dot inversion driver * Single-sided mounting possible (loaded with slim TCP)
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16635N-xxx
The TCP's external shape is customized. To order your TCP's external shape, please contact a NEC salesperson.
Document No. S11420EJ1V0DS00 (1st edition) Date Published September 1996 P Printed in Japan
(c)
1996
PD16635
1. BLOCK DIAGRAM
STHR R/L CLK STB
40-bit bidirectional shift register C1 C2 C39 C40
STHL VDD1 VSS1
D00 - 05 D10 - 15 D20 - 25 D30 - 35 D40 - 45 D50 - 55
Data register
POL
Latch
VDD2 Level shifter VSS2
V0 - V9
D/A converter
Voltage follower output
S1
S2
S3
S240
2
PD16635
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1 S2 S239 S240
V4 V5 V9
*****
*****
V0 Multiplexer
5
6-bit D/A converter 5
POL
POL L H
S2n-1 V0 to V4 V5 to V9
S2n V5 to V9 V0 to V4
S2n-1 (odd output), S2n (even output) n = 1, 2, *****, 120
3
PD16635
3. PIN CONFIGURATION (PD16635N-xxx)
VSS2 VDD2 VSS1 R/L POL STB D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 STHL V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 CLK STHR D30 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 TEST VDD1 VDD2 VSS2
S240 S239 S238 S237
S4 S3 S2 S1
This figure shows the pin connection, not a TCP package.
4
PD16635
4. PIN FUNCTIONS
Pin Symbol S1 to S240 D00 to D05 D10 to D15 D20 to D25 D31 to D35 D40 to D45 D50 to D55 R/L Shift direction switching input These refer to the start pulse input/output pins when cascades are connected. The shift directions of the shift registers are as follows. R/L = H: STHR input, S1 S240, STHL output R/L = L : STHL input, S240 S1, STHR output R/L = H: Becomes the start pulse input pin. R/L = L : Becomes the start pulse output pin. R/L = H: Becomes the start pulse output pin. R/L = L : Becomes the start pulse input pin. Refers to the shift register's shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 40th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-stage driver. The initial-stage driver's 40th clock becomes valid as the next-stage driver's start pulse is input. If 42 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB's rising edge. The contents of the data register are transferred to the latch at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL = L; The S2n-1 output uses V0 to V4 as the reference supply; and the S2n output uses V5 to V9 as the reference supply. POL = H; The S2n-1 output uses V5 to V9 as the reference supply; and the S2n output uses V0 to V4 as the reference supply. S2n - 1 indicates the odd output; and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB's rising edge. Input the -corrected power supplies from outside. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 Set it to "OPEN". 3.3 V 0.3 V 11.0 V to 13.5 V Grounding Grounding Pin Name Driver output Display data input Description The D/A converted 64-gray-scale analog voltage is output. The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). DX0: LSB, DX5: MSB
STHR STHL CLK
Right shift start pulse input/output Left shift start pulse input/output Shift clock input
STB
Latch input
POL
Polarity input
V0 to V9
-corrected power supplies
TEST VDD1 VDD2 VSS1 VSS2
Test pin Logic power supply Driver power supply Logic ground Driver ground
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is possible.) 2. To stabilize the supply voltage, please be sure to insert a 0.1 F bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 F is also advised between the -corrected power supply terminals (V0, V1, V2, ***, V9) and VSS2.
5
PD16635
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD's counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors r0 to r62 are so designed that the ratios between the LCD panel's -corrected voltages and V0' to V63' and V0" to V63" are roughly equal; and their respective resistance values are as shown on page 9. Among the 5-by-2 -corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective five -corrected voltages of V0 to V4 and V5 to V9. If fine gray scale voltage precision is not necessary, the voltage follower circuit supplied to the -corrected power supplies V1 to V3 and V6 to V8 can be deleted. Figure 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2. Figures 2-1 and 22 show the relationship between the input data and the output data. Table 1 shows the resistance values of the resistor strings. This driver IC is designed for single-sided dot inversion mounting. Therefore, it cannot be used in doublesided mounting. Figure 1. Relationship Between Input Data and Output Voltage
VDD2 V0 8 V1 24 V2 24 V3 7 V4 VCOM V5 7 V6 24 V7 24 V8 8 V9 0.2 V VSS2 00 08 10 18 20 28 30 38 3F Input data (HEX)
0.2 V
Split interval
6
PD16635
Resistor Strings Figure 2-1. Relationship Between Input Data and Output Voltage: VDD2 > V0 > V1 > V2 > V3 > V4 > V5
V0 r0 V1' r1 V2' r2 V3' r3 V4' r4 V5' r5 V6' r6 V7' r7 V1 r8 V9' r9 V8' V0' Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H V31' r31 V2 r32 V33' r33 V32' 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63' Output Voltage V0 V1 + (V0 - V1) x 4500/5300 V1 + (V0 - V1) x 3700/5300 V1 + (V0 - V1) x 2900/5300 V1 + (V0 - V1) x 2200/5300 V1 + (V0 - V1) x 1500/5300 V1 + (V0 - V1) x 900/5300 V1 + (V0 - V1) x 400/5300 V1 V2 + (V1 - V2) x 3600/4000 V2 + (V1 - V2) x 3300/4000 V2 + (V1 - V2) x 3000/4000 V2 + (V1 - V2) x 2700/4000 V2 + (V1 - V2) x 2400/4000 V2 + (V1 - V2) x 2200/4000 V2 + (V1 - V2) x 2000/4000 V2 + (V1 - V2) x 1800/4000 V2 + (V1 - V2) x 1600/4000 V2 + (V1 - V2) x 1400/4000 V2 + (V1 - V2) x 1300/4000 V2 + (V1 - V2) x 1200/4000 V2 + (V1 - V2) x 1100/4000 V2 + (V1 - V2) x 1000/4000 V2 + (V1 - V2) x 900/4000 V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x 800/4000 700/4000 600/4000 500/4000 400/4000 300/4000 200/4000 100/4000
r30
r54 V55' r55 V3 r56 V57' r57 V58' r58 V59' r59 V60' r60 V61' r61 V62' r62 V4 r4-5 V5 V63' 9 k V63'' V56'
V2 V3 + (V2 - V3) x 2600/2700 V3 + (V2 - V3) x 2500/2700 V3 + (V2 - V3) x 2400/2700 V3 + (V2 - V3) x 2300/2700 V3 + (V2 - V3) x 2200/2700 V3 + (V2 - V3) x 2100/2700 V3 + (V2 - V3) x 2000/2700 V3 + (V2 - V3) x 1900/2700 V3 + (V2 - V3) x 1800/2700 V3 + (V2 - V3) x 1700/2700 V3 + (V2 - V3) x 1600/2700 V3 + (V2 - V3) x 1500/2700 V3 + (V2 - V3) x 1400/2700 V3 + (V2 - V3) x 1300/2700 V3 + (V2 - V3) x 1200/2700 V3 + (V2 - V3) x 1100/2700 V3 + (V2 - V3) x 1000/2700 V3 + (V2 - V3) x 900/2700 V3 + (V2 - V3) x 800/2700 V3 + (V2 - V3) x 700/2700 V3 + (V2 - V3) x 600/2700 V3 + (V2 - V3) x 400/2700 V3 + (V2 - V3) x 200/2700 V3 V4 + (V3 - V4) x 2300/2500 V4 + (V3 - V4) x 2100/2500 V4 + (V3 - V4) x 1800/2500 V4 + (V3 - V4) x 1500/2500 V4 + (V3 - V4) x 1200/2500 V4 + (V3 - V4) x 800/2500 V4
Caution
V4 and V5 are interconnected inside the IC by resistors r4-5 (9 k).
7
PD16635
Resistor Strings Figure 2-1. Relationship Between Input Data and Output Voltage: V4 > V5 > V6 > V7 > V8 > V9 > VSS2
Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H V9'' r8 V8 r7 V7'' r6 V6'' r5 V5'' r4 V4'' r3 V3'' r2 V2'' r1 V1'' r0 V9 V0'' V8'' 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0'' V1'' V2'' V3'' V4'' V5'' V6'' V7'' V8'' V9'' V10'' V11'' V12'' V13'' V14'' V15'' V16'' V17'' V18'' V19'' V20'' V21'' V22'' V23'' V24'' V25'' V26'' V27'' V28'' V29'' V30'' V31'' V32'' V33'' V34'' V35'' V36'' V37'' V38'' V39'' V40'' V41'' V42'' V43'' V44'' V45'' V46'' V47'' V48'' V49'' V50'' V51'' V52'' V53'' V54'' V55'' V56'' V57'' V58'' V59'' V60'' V61'' V62'' V63'' Output Voltage V9 V9 + (V8 - V9) x 800/5300 V9 + (V8 - V9) x 1600/5300 V9 + (V8 - V9) x 2400/5300 V9 + (V8 - V9) x 3100/5300 V9 + (V8 - V9) x 3800/5300 V9 + (V8 - V9) x 4400/5300 V9 + (V8 - V9) x 4900/5300 V8 V8 + (V7 - V8) x 400/4000 V8 + (V7 - V8) x 700/4000 V8 + (V7 - V8) x 1000/4000 V8 + (V7 - V8) x 1300/4000 V8 + (V7 - V8) x 1600/4000 V8 + (V7 - V8) x 1800/4000 V8 + (V7 - V8) x 2000/4000 V8 + (V7 - V8) x 2200/4000 V8 + (V7 - V8) x 2400/4000 V8 + (V7 - V8) x 2600/4000 V8 + (V7 - V8) x 2700/4000 V8 + (V7 - V8) x 2800/4000 V8 + (V7 - V8) x 2900/4000 V8 + (V7 - V8) x 3000/4000 V8 + (V7 - V8) x 3100/4000 V8 + (V7 - V8) x 3200/4000 V8 + (V7 - V8) x 3300/4000 V8 + (V7 - V8) x 3400/4000 V8 + (V7 - V8) x 3500/4000 V8 + (V7 - V8) x 3600/4000 V8 + (V7 - V8) x 3700/4000 V8 + (V7 - V8) x 3800/4000 V8 + (V7 - V8) x 3900/4000 V7 V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x V7 + (V6 - V7) x 100/2700 200/2700 300/2700 400/2700 500/2700 600/2700 700/2700
V4 r4-5 V5 r62 r61
V63' 9 k V63'' V62'' V61'' r60 V60'' r59 V59'' r58 V58'' r57 V57'' r56
V6 r55 r54
V56'' V55''
r33 V33'' r32 V7 r31 V31'' r30 V32''
r9
V7 + (V6 - V7) x 800/2700 V7 + (V6 - V7) x 900/2700 V7 + (V6 - V7) x 1000/2700 V7 + (V6 - V7) x 1100/2700 V7 + (V6 - V7) x 1200/2700 V7 + (V6 - V7) x 1300/2700 V7 + (V6 - V7) x 1400/2700 V7 + (V6 - V7) x 1500/2700 V7 + (V6 - V7) x 1600/2700 V7 + (V6 - V7) x 1700/2700 V7 + (V6 - V7) x 1800/2700 V7 + (V6 - V7) x 1900/2700 V7 + (V6 - V7) x 2000/2700 V7 + (V6 - V7) x 2100/2700 V7 + (V6 - V7) x 2300/2700 V7 + (V6 - V7) x 2500/2700 V6 V6 + (V5 - V6) x 200/2500 V6 + (V5 - V6) x 400/2500 V6 + (V5 - V6) x 700/2500 V6 + (V5 - V6) x 1000/2500 V6 + (V5 - V6) x 1300/2500 V6 + (V5 - V6) x 1700/2500 V5
Caution
V4 and V5 are interconnected inside the IC by resistors r4-5 (9 k).
8
PD16635
Ladder Resistance Values (r0 to r62): Reference Value
Resistor Name V0, V9 r0 r1 r2 r3 r4 r5 r6 V1, V8 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 V2, V7 r31
Resistance Value () 800 800 800 700 700 600 500 400 400 300 300 300 300 200 200 200 200 200 100 100 100 100 100 100 100 100 100 100 100 100 100 100
Resistor Name r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 Total
Resistance Value () 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 200 200 200 200 200 300 300 300 400 800 14500 V4, V5 V3, V6 V2, V7
9
PD16635
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) R/L = H (Right shift)
Output Data
S1 D00 to D05
S2 D10 to D15
S3 D20 to D25
S4 D30 to D35
S5 D40 to D45
*** ***
S239 D40 to D45
S240 D50 to D55
R/L = L (Left shift)
Output Data
S1 D00 to D05
S2 D10 to D15
S3 D20 to D25
S4 D30 to D35
S5 D40 to D45
*** ***
S239 D40 to D45
S240 D50 to D55
POL L H
S2n-1 V0 to V4 V5 to V9
S2n V5 to V9 V0 to V4
S2n-1 (Odd output), S2n (Even output) n = 1, 2, *****, 120
7.
RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB rising edge.
STB
POL
S2n-1
Selected voltage of V0 to V4
Selected voltage of V5 to V9
Selected voltage of V0 to V4
S2n
Selected voltage of V5 to V9 Hi-Z Hi-Z
Selected voltage of V0 to V4 Hi-Z
Selected voltage of V5 to V9
10
PD16635
Absolute Maximum Ratings (TA = 25 C, V
SS1
= VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage Logic Part Input Voltage Driver Part Input Voltage Logic Part Output Voltage Driver Part Output Voltage Operating Temperature Range Storage Temperature Range
Symbol VDD1 VDD2 VI1 VI2 VO1 VO2 TA Tstg.
Rating -0.5 to +6.5 -0.5 to +15.0 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 -10 to +75 -55 to +125
Unit V V V V V V C C
Recommended Operating Range (TA = -10 to +75 C, V
SS1
= VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage High-Level Input Voltage Low-Level Input Voltage
Symbol VDD1 VDD2 VIH VIL V0 to V9 VO fmax.
MIN. 3.0 11.0 0.8 VDD1 0 VSS2 + 0.1 VSS2 + 0.2 33
TYP. 3.3 13.0
MAX. 3.6 13.5 VDD1 0.2 VDD1 VDD2 - 0.1 VDD2 - 0.2
Unit V V V V V V MHz
-Corrected Voltage
Driver Part Output Voltage Maximum Clock Frequency
Electrical Specifications (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 13.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Input Leak Current High-Level Output Voltage Low-level Output Voltage Symbol IL VOH VOL STHR (STHL), IO = 0 mA STHR (STHL), IO = 0 mA V0 - V9 = 10 V IVOH IVOL VX - VOUT = 6 V VX - VOUT = -6 V 0.3 V0, V9 0.3 VDD1 - 0.1 0.1 0.6 -0.3 Condition MIN. TYP. MAX. 1.0 Unit
A
V V mA mA mA
-Corrected Supply Current
Driver Output Current
VX refers to the output voltage of analog output pins S1 to S240. VOUT refers to the voltage applied to analog output pins S1 to S240.
11
PD16635
Electrical Specifications (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 13.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Output Voltage DeviationNote 1 Symbol VO VAV Condition Input data: 00H to 3FH Input data: 00H to 3FH MIN. TYP. 5 10 MAX. 20 Unit mV mV
Average Output Voltage VariationNote 2 Output Voltage Range Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption
VO IDD1
Input data: 00H to 3FH VDD1; when with no loadNotes 3, 4
0.2 1.0
VDD2 - 0.2 6.0
V mA
IDD2
VDD2; when with no loadNotes 3, 4
3.5
9.0
mA
Notes 1. The output voltage deviation refers to the voltage difference between adjoining output pins when the display data is the same (within the chip). 2. The average output voltage variation refers to the average output voltage difference between chips. The average output voltage refers to the average voltage between chips when the display data is the same. 3. The STB cycle is defined to be 30 s at fCLK = 25 MHz. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 4. Refers to the current consumption per driver when cascades are connected under the assumption of SVGA single-sided mounting (10 units). Switching Characteristics (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 13.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Start Pulse Delay Time Driver Output Delay Time 1 Driver Output Delay Time 2 Driver Output Delay Time 3 Driver Output Delay Time 4 Input Capacitance 1 Symbol tPLH1 tPHL2 tPHL3 tPLH2 tPLH3 C1 CL = 25 pF CL = 50 pF, R = 50 k CL = 50 pF, R = 50 k CL = 50 pF, R = 50 k CL = 50 pF, R = 50 k STHR, STHL excluded TA = 25 C Input Capacitance 2 C2 STHR, STHL TA = 25 C 5 15 pF Condition MIN. TYP. 10 7 13 7 13 5 MAX. 15 11 17 11 17 15 Unit ns
s s s s
pF
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PD16635
Conditions Required for Timing (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter Clock Pulse Width Clock Pulse Low Period Clock Pulse High Period Data Setup Time Data Hold Time Start Pulse Setup Time Start Pulse Hold Time Start Pulse Low Period STB Pulse Width Data Invalid Period Final Data Timing CLK-STB Time STB-CLK Time Time Between STB and Start Pulse POL-STB Time STB-POL Time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSPL PWSTB tINV tLDT tCLK-STB tSTB-CLK tSTB-STH CLK STB STB CLK STB STHR POL or STB STB POL or Condition MIN. 30 6 6 6 6 6 6 6 1 1 2 6 6 60 TYP. MAX. Unit ns ns ns ns ns ns ns ns
s
CLK CLK ns ns ns
tPOL-STB tSTB-POL
-5 6
ns ns
13
PD16635
Switching Characteristics Waveform (R/L = H) Unless otherwise specified, the input level is defined to be 0.5 VDD1. In ( ): R/L = L
(1) Initial-Level Driver's Input/Output Waveform
PWCLK CLK PWCLK (H) 1 PWCLK (L) 2 tf
90 % 90 % 10 % 10 %
tr 3 VDD1 VSS1
tSETUP1 INVALID INVALID 1
tHOLD1 2 VDD1 VSS1
DXX
tHOLD2 tSETUP2 tHOLD2 VDD1 STHR (IN) (STHL) VSS1
(2) Second- to Final-Level Drivers's Input/Output Timing
40 CLK 41 1 2 3 40 1 41 VDD1 VSS1
VDD1 Dxx 39 40 1 2 39 40 VSS1
tPLH1 Initial-level output STHR (IN) (STHL) STHL (OUT) (STHR)
tSETUP2 VDD1 tPLH1 tSETUP2 VSS1 VDD1 VSS1
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PD16635
(3) Driver Output Timing
VDD1 DXX 40 INVALID VSS1 tHOLD2 CLK 41 42 43 1 VDD1 VSS1 tINV tLDT tCLK-STB tSTB-CLK PWSTB VDD1 STB VSS1 tPOL-STB tSTB-POL VDD1 POL VSS1 tSTB-STH tSETUP2 tHOLD2
STHR (IN) (STHL) tSPL Hi-Z tPHL2 tPHL3
VDD1 VSS1
VDD2 Sn VX tPLH3 tPLH2 VX Sm Hi-Z
VSS2
VX refers to the final output voltage. tPLH2 and tPHL2 refer to the time required to reach an output precision level of 10 % (0.1 VX); and tPLH3 and tPHL3 refer to the time required to reach an output precision level of 6 bits.
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PD16635
RECOMMENDED CONDITIONS FOR INSTALLATION
This product should be installed under the following recommended conditions. Consult one of our sales representatives for installation under conditions other than those recommended.
Installation condition Thermocompression bonding
Installation method Soldering
Condition Heat with heating tool at 300 C to 350 C under pressure of 100 g (per pin) for 2 to 3 seconds Temporary adhesion at 70 C to 100 C under pressure of 3 to 8 kg/cm2 for 3 to 5 seconds Permanent adhesion at 165 C to 180 C under pressure of 25 to 45 kg/cm2 for 30 to 40 seconds (when aeolotropic conductive film SUMIZAC1003 from Sumitomo Bakelite Co., Ltd. is used)
ACF (sheet-type adhesive agent)
Caution
For installation conditions for the ACF part, contact the ACF manufacturer beforehand. Do not mix different installation methods.
REFERENCE
Document name NEC semiconductor device reliability/quality control system Quality grade on NEC semiconductor devices Semiconductor device package manual Guide to quality assurance for semiconductor devices Semiconductor selection guide Document No. IEI-1212 C11531E IEI-1213 MEI-1202 X10679E
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PD16635
[MEMO]
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[MEMO]
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[MEMO]
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